1. Field of the Invention
The present invention relates to techniques for performing computer aided design of large scale integrated circuits and more particularly to an apparatus for a hierarchical circuit data base optimizing apparatus and a hierarchical circuit data base optimizing method, whereby information relevant to hierarchical circuits is maintained in the form of a data base for executing such design with high efficiency, in case such circuit design is to be made in a hierarchical structure, such a data base being thereby optimized.
2. Description of Related Art
Computer aided design (hereinafter referred to as "CAD") has become indispensable along with the growing complexity of design work required for large scale integrated circuits (hereinafter referred to as "LSI"), and, in fact, CAD techniques are absolutely necessary for executing the techniques generally known as "silicon compilation" and "logic synthesis" applied to the formation of layout patterns of such circuits on the basis of logical specifications for LSI.
Thus, attempts have hitherto been made, in respect of the design of LSI circuits, at performing circuit design work on LSI with ease by storing information relevant to the circuits, such as interfaces between circuits, in the form of a data base (called "circuit data base") and utilizing such a circuit data base.
Above all, such attempts have been made at automatically executing circuit design work, using such a data base, which is structured in the form of a hierarchical data base composed of information relevant to such circuits, by grasping an arrangement of such circuits and their connections in terms of a hierarchical structure, on the ground that it can thereby be made possible to achieve a reduction of the memory area for a circuit data base and to attain an improvement on the processing operations on the occasion of the execution of the circuit design on LSI. The technique for developing an arrangement of functions on an integrated circuit through utilization of such a hierarchical circuit data base has already become a publicly known technique, which is described, for example, in the Japanese Patent Unexamined Publication No. Sho. 64-80040.
However, the above-mentioned technique for designing an LSI circuit through utilization of a generally known prior art circuit data base as described above has a tendency towards an increase of the cost needed for the wiring part in the overall area of an LSI along with the enlargement of the scale of such a circuit, and there has therefore been a desire for a technique which optimizes such a circuit data base in a more efficient manner. Yet, there has been a problem that the optimization of such a data base presents difficulty.
In the meanwhile, CAD tools operating through utilization of such techniques as silicon compilation and logical synthesis are composed of abstracted statements of logics, so that designing engineers will not necessarily be able to grasp all the control signals and that such tools present difficulty in the optimization of a circuit data base in any such manner as to minimize the interface signals.
Also, the use of a hierarchical circuit data base in the conventional hierarchical structure mentioned above presents the problem that it is left entirely to the designing engineer's discretion to determine a hierarchical structure for a given circuit, with no automation having yet been accomplished for the process of determining a hierarchical structure for a circuit, also that progressive enlargements and growing complexity of such circuits have resulted in a situation in which the relations among such circuits as viewed from the standpoint of their connections in the formation of a hierarchical structure are not necessarily in any optimized condition for the purpose of minimizing the interface signals, and further that the optimizing process is difficult to perform by manual operation.
That is to say, the use of a conventional hierarchical circuit data base as mentioned above would be liable to be faced with difficulty in determining the hierarchical relations among partial circuits, or to determine the hierarchical strata to which the lower-ranking modules belong, in order to achieve the maximum reduction of the number of the interface signals among units of circuit groups.
In order to describe the above-mentioned problems more clearly, a description will be made in respect of two simple examples, with reference to drawings. FIG. 6 is a chart which illustrates the procedure for determining the hierarchical positions of a first module 20 and a second module 21.
FIG. 6 shows that the first module 20 and the second module 21 are arranged in such a manner that they will be at the same hierarchical level, and, additionally, a sub-module A22 is arranged so as to belong to the area in the first module 20, so that the sub-module A22 will be positioned at a hierarchical level directly below that of the first module 20.
Then, the Sub-module A22 has m-lines of wires for interface signals running in the direction of the inside area of the first module 20 and also has n-lines of wires for the interface signals between the Sub-module A22 and the second module 21.
If the relation, m&lt;n, holds true in this case, the circuit construction shown in FIG. 6 will attain a reduction of the number of wires between the first module 20 and the second module 21 and will possibly attain a reduction of the wiring area as a whole with a circuit structure with the sub-module A22 is arranged inside the second module 21 as shown in FIG. 7. Such a reduction of the wiring area in the circuit construction as a whole can be accomplished because it is possible to form the wiring area between modules in a smaller size, even if the number of wires in the inside area of a module is increased, since the wiring in the inside area of a module can generally be formed in a length shorter than that of wiring between modules.
The example given in FIG. 8 illustrates a more complex case. FIG. 8, which is a drawing for illustration of a procedure for determining the hierarchical positions of three circuit modules. As shown in FIG. 8, a third module 23, a fourth module 24, and a fifth module 27 are arranged in such a way that they are positioned at the same hierarchical level, and the third module 23 includes a sub-module B25 while the fourth module 24 includes a sub-module C26.
The sub-module B25 has t-lines of wires for interface signal directed toward the inside area of the third module 23 and has p-lines of wires and r-lines of wires for interface signals, these groups of wires respectively leading towards the inside area of the sub-module C26 and the fifth module 27.
Additionally, the sub-module C26 has q-lines of wires for interface signals leading therefrom into the inside area of the fourth module 24 while it has p-lines of wires and s-lines of wires for connections thereof with the sub-module B25 and a module 27.
Now, if the relationship, (t+q)&lt;(p+r+s), holds true in this case, the circuit construction shown in FIG. 8 will be able to attain a reduction of the wiring area, for the same reason as that given in the case of the circuit construction shown in FIG. 6, when the sub-module B25 and the sub-module C26 are arranged in the inside area of the module 27, as shown in FIG. 9.
These examples merely present very simple hierarchical structures, and yet the conventional hierarchical circuit data base structure is faced with the problem that it would be an extremely difficult task to apply the technique for determining the hierarchical positions of circuit modules to all the circuits by manual operation in the manner described above because such an actual hierarchical circuit data base for an LSI will be very large in scale and very complex in structure.